Error-Tolerant Computing Using Booth Squarer Design and Analysis

Abstract

"Approximate computing" is a design technique that sacrifices computational correctness in order to obtain high performance and low power consumption. Approximate Booth multiplier structures are the focus of this investigation in this thesis. The approximate multiplier for errors resulting from the approximate radix-4 Booth encoding, the approximate regular partial product array, and the approximate 4-2 compressor is estimated using a probabilistic error model. The NMEDs of 8-bit and 16-bit approximation designs can be determined using the proposed methodology. Simulated findings show that the error model and its related framework are accurate, proving the validity of the analytical frameworks used.